1. Field
Example embodiments relate to an electronic circuit, and particularly, to a delay locked loop circuit and operation method thereof.
2. Description
A delay locked loop circuit may compare a phase of an input clock signal with a phase of a feedback clock signal and may generate an error signal proportional to the phase difference. The delay locked loop circuit may be used in semiconductor circuits such as semiconductor memory devices or the like.
The delay locked loop circuit may include a phase detector, a charge pump circuit, a loop filter that may be implemented using a low pass filter, for example, and a variable delay circuit.
The phase detector may detect the phase difference between an input clock signal and a feedback clock signal output from the variable delay circuit. The charge pump circuit may charge or discharge an electric charge of the loop filter, in response to the output signal of the phase detector. The variable delay circuit may delay the input clock signal to output the feedback clock signal synchronized with the input clock signal, in response to a voltage corresponding to the electric charge that is charged in or discharged from the loop filter.